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Computer Science 2 HSC Science (Computer Science) 12th Standard Board Exam Maharashtra State Board Syllabus 2025-26

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Maharashtra State Board 12th Standard Board Exam Computer Science 2 Syllabus - Free PDF Download

Maharashtra State Board Syllabus 2025-26 12th Standard Board Exam: The Maharashtra State Board 12th Standard Board Exam Computer Science 2 Syllabus for the examination year 2025-26 has been released by the MSBSHSE, Maharashtra State Board. The board will hold the final examination at the end of the year following the annual assessment scheme, which has led to the release of the syllabus. The 2025-26 Maharashtra State Board 12th Standard Board Exam Computer Science 2 Board Exam will entirely be based on the most recent syllabus. Therefore, students must thoroughly understand the new Maharashtra State Board syllabus to prepare for their annual exam properly.

The detailed Maharashtra State Board 12th Standard Board Exam Computer Science 2 Syllabus for 2025-26 is below.

Academic year:

Maharashtra State Board 12th Standard Board Exam Computer Science 2 Revised Syllabus

Maharashtra State Board 12th Standard Board Exam Computer Science 2 and their Unit wise marks distribution

Maharashtra State Board 12th Standard Board Exam Computer Science 2 Course Structure 2025-26 With Marking Scheme

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Syllabus

1 Introduction to Microprocessors and Organization of 8085
  • Evolution of Microprocessors  
    • First generation
    • Second generation
    • Third generation
    • Fourth generation
  • Microprocessor & its related terms  
    • Definition
    • Arithmetic/Logic unit (ALU)
    • Registers & Control unit
    • Memory & System Bus
    • Primary function of the CPU of a microcomputer 
    • Block diagram of ALU
  • Block Diagram of Generic Microprocessor  
    • Address & Data Bus
    • Data Address & Instruction Register
    • Instruction Decoder
    • Arithmetic and Logic unit(ALU) & Accumulator
    • Program Counter & Stack Pointer
    • Timing and control unit
    • Control Inputs and Outputs
    • Bus Buffers and Latches
    • Status Register
  • 8085 Microprocessor  
    • The 8085 Pin Diagram and Functions
    • Multiplexed Address/Data Bus
    • Control and Status signals
    • Externally Initiated signals
    • Power supply and clock frequency & Serial I/O Ports
    • Functional Block diagram of 8085
    • Flags
    • Register Array
    • Program Counter (PC) & Stack Pointer (SP)
    • Interrupts
  • Instruction Cycle  
    • T State’s
    • Machine Cycle
  • Addressing Modes in 8085  
    • Direct Addressing
    • Register Addressing Mode
    • Register Indirect Addressing
    • Immediate Addressing
    • Implied Addressing
2 Instruction Set and Programming of 8085
  • Instruction Cycle  
    • T State’s
    • Machine Cycle
  • Addressing Modes in 8085  
    • Direct Addressing
    • Register Addressing Mode
    • Register Indirect Addressing
    • Immediate Addressing
    • Implied Addressing
  • Data Transfer (Copy) group of Instruction  
    • MOV r1, r2; MOV r, M & MOV M, r
    • MVI r, data & MVI M, data
    • LXI rp, data 16 (Load register pair immediate)
    • LDA addr (Load accumulator direct) & STA addr (Store Accumulator Direct)
    • LHLD addr(Load Hand L direct) & SHLD addr (Store H and L direct)
    • LDAX rp (Load accumulator indirect) & STAX rp (Store accumulator indirect)
    • XCHG (Exchange Hand L with D and E) 
    • IN & OUT
  • Arithmetic Group of Instructions  
    • ADD r (Add Register); ADD M (Add memory) & ADI data (Add immediate)
    • ADC r (Add register with carry); ADC M (Add memory with Carry) & ACI data (Add Immediate with carry)
    • SUB r (Subtract Register); SUB M (Subtract memory) & SUI data (Subtract immediate) 
    • SBB r (Subtract register with borrow); SBB M (Subtract Memory with borrow) & SBI data (Subtract immediate with borrow) 
    • INR r (Increment register) & INR M (Increment register)
    • DCR r (Decrement Register) & DCR M (Decrement Memory)
    • INX rp (Increment register pair) & DCX rp (Decrement register pair)
    • DAD rp (Add register pair to H and L) 
    • DAA-DECIMAL ADJUST ACCUMULATOR
  • Logical Instructions  
    • ANA r (AND register) ANA M (AND memory) & ANI data (AND immediate)
    • XRA r (Exclusive OR Register); XRA M (Exclusive OR memory) & XRI data (Exclusive OR immediate)
    • ORA r (OR register); ORA M (OR memory) & ORI data (OR immediate)
    • CMP r (Compare Register) & CMP M (Compare Memory) 
    • RLC (Rotate Left) & RRC (Rotate Right)
    • RAL (Rotate left through carry) & RAR (Rotate Right through carry)
    • CMA (Complement accumulator); CMC (Complement carry) & STC (Set carry)
  • Branch Instructions  
    • JMP addr & Jcondition addr
    • CALL addr & Ccondition addr 
    • RET(Return) & Rcondition (Conditional return)  
    • RST n (Restart)
    • PCHL (Jump H and L indirect - move H and L to PC) 
  • Stack and Queue in Data Structure  
  • Assembly Language Programs  
    • General Format of Assembly language Programs
3 Introdcution to Inted X-86 Family
4 Introduction to Microcontroller
5 Networking Technology
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