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Question
The output of an OR gate is connected to both the inputs of a NAND gate Draw the logic circuit of this combinaion of getes and write its truth table.
Solution 1
Both the inputs of the NAND gates are joined to form a single input. Therefore, it behaves like a NOT gate.
| A | B | A + B | `overline(A+B)` |
| 0 | 0 | 0 | 1 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 1 | 0 |
Solution 2
Both the inputs of the NAND gates are joined to form a single input. Therefore, it behaves like a NOT gate.
| A | B | A + B | `overline(A+B)` |
| 0 | 0 | 0 | 1 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 1 | 0 |
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