Logical Instructions

ANA r (AND register);  ANA M (AND memory) & ANI data (AND immediate)

ANA r:  (A) <-  (A) /\ (r),    

The contents of register r is logically AND ed with the content of accumulator. The result is placed in accumulator. The cy flag is cleared and AC is set. This is one byte instruction. 

Addressing Mode: Register Addressing.   

 ANA M: (A) <- (A) /\ ((H) (L)),  

Same as previous instruction; the difference is the content to be AND ed is present in a memory location pointed by HL Pair. The CY flag is cleared and AC is set. This is one byte instruction. Addressing Mode: Register indirect.                       

ANI data: (A) <- (A) /\ (byte 2),   

Two byte instruction. Here the content to be AND ed is provided in the second byte of  instruction. The CY flag is cleared and AC is set.  Addressing Mode: Immediate Addressing. 

XRA r (Exclusive OR Register); XRA M (Exclusive OR memory) & XRI data (Exclusive OR immediate) 

XRA r: (A) <- (A) ⊕  (r), 

The content of register r is exclusive OR'ed with the content of accumulator. The result is placed in accumulator. The CY and AC flags are cleared. This is one byte instruction. Addressing Mode: Register Addressing. 

XRA M: (A) <- (A) ⊕ [(H) (L)], 

Everything same as the previous instruction the only difference lies in the content which is to exclusive OR’ed being present in a memory location pointed by HL Pair. Addressing Mode: Register Indirect. 

XRI data: (A) <- (A) ⊕ (byte 2), 

This is a two byte instruction. The content to be exclusive OR’ed is present is the second byte instruction. The CY and AC flags are cleared. The result is place in accumulator. . Addressing Mode: Immediate Addressing. 

ORA r (OR register); ORA M (OR memory) & ORI data (OR immediate) 

ORA r: (A) <- (A) V r, 

The content of the register r is inclusive OR' ed with the content of the accumulator. The result is placed in the accumulator. The CY and AC flags are cleared. Addressing Mode: Register 

ORA M: (A) <- (A) v ((H) (L)), 

Everything same as the previous instruction the only difference lies in the content which is to  OR’ed being present in a memory location pointed by HL Pair. Addressing Mode: Register Indirect. 

ORI data: (A) <- (A) v (byte 2), 

This is a two byte instruction. The content to be  OR’ed is present is the second byte instruction. The CY and AC flags are cleared. The result is place in accumulator. Addressing Mode: Immediate Addressing. 

CMP r (Compare Register) & CMP M (Compare Memory) 

CMP r: (A) - (r), 

The content of register r is subtracted from the accumulator without changing the accumulator. Condition flags are updated: the Z flag is set to 1 if (A) equals (r), the CY flag is set to 1 if (A) is less than (r) and none of CY or Zero Flag is set when (A)>(r). , Addressing : Register Addressing. 

CMP M: (A) - ((H) (L)) 

Everything is same as in the previous instruction just the content to be compared is in a memory location pointed by HL Pair.  Addressing Mode: Register Indirect. 

        RLC (Rotate Left) & RRC (Rotate Right) 

Note: RLC: (A_{n+ 1}) <- (A_n);       (A₀) <- (A₇)  

                           (CY) <-  (A₇) 

The content of the accumulator is rotated left one position. The low order bit and the CY flag are both set to the value shifted out of the high order bit position. Only the CY flag is affected. This is one byte instruction.

RRC: (A_n) <- (A_{n +1}) ;              (A₇) <- (A₀)  

            (CY) <- (A₀). 

The content of accumulator is rotated right one position. The higher order bit and the CY flag are both set to the value shifted out of the low order bit position. Only the CY flag is affected. This is one byte instruction. 

  RAL (Rotate left through carry) & RAR (Rotate Right through carry) 

RAL:             (A_{n +1}) <- (A_n); (CY) <-(A₇) 

                     (A₀) <- (CY) 

The content of accumulator is rotated left one position through the CY flag. The low-order bit is set equal to the CY flag and the CY flag is set to the value of shifted out of the high order bit. Only the cy flag is affected

RAR:       (A_n) <- (A_{n+ 1)} ;   ( cy) <- (A₀)  

              (A₇) <- (cy) 

The content of the accumulator is rotated right on position through the CY flag. The high order bit is set to the CY flag and the CY flag is set to the value shifted out of the low order bit. Only the cy flag is affected.

CMA (Complement accumulator); CMC (Complement carry) & STC (Set carry) 

CMA: (A) <- (A bar)

The contents of accumulator are complemented (Zero bits become 1, one bits becomes 0). No flags are affected . This is one byte instruction. 

CMC: (cy) <- (cy bar)

The carry flag is complemented. No other flags are affected 

STC: (cy) <- 1. 

Carry flag is set to 1. No other flags are affected.